
R
SelectMAP Interface
Table 4-4:
CPLD Pin Listing (Continued)
Pin
Number
32
33
34
35
36
37
Net Name
RTR (1)
PCIW_EN (1)
FPGA_RDWR_B
VCC2V5
CPLD_SPARE3
PCIE_RST
Direction
I
I
O
I
I/O
I
Pin Type
IO/GOE2
IO/GOE3
IO/GOE4
VAUX
IO18
IO19
Description
Input connected from Pin F16 of FPGA
Input connected from Pin F11 of FPGA
Output connected to RDWR_B pin of FPGA
2.5V auxiliary power
Spare I/O connected to FPGA pin H9
Active-Low RESET input for PCI Express from
P13-A11
38
FLASH_CE1_B
O
IO20
Output connected to the CE pin of Platform Flash
U15
39
FLASH_REV_SEL0
O
IO21
Output connected to the REV_SEL0 pin of
Platform Flash devices
40
FLASH_REV_SEL1
O
IO22
Output connected to the REV_SEL1 pin of
Platform Flash devices
41
BUSY_TO_FLASH_B
O
IO23
Output connected to the BUSY pin of Platform
Flash devices
42
FLASH_CE_B
O
IO24
Output connected to the CE pin of Platform Flash
U1
43
FLASH_CF_B
O
IO/GC2
Output connected to the CF pin of Platform Flash
devices
44
FLASH_OE_RESET_B
O
IO/GC3
Output connected to the OE/RESET pin of
Platform Flash devices
Notes:
1. The Net Names and Directions for pins 29 through 33 were chosen to support a specific PCI/PCI-X design as described in
“CPLD2. All CPLD I/O are 2.5V LVCMOS.
Table 4-5:
Pin Listing for Platform Flash
Pin
Number
C1
Net Name
BUSY_TO_FLASH_B
Direction
I
Pin Type
BUSY
Description
Active-Low Busy signal connected from CPLD Pin
41
G1
B4
CPLD_TDO
FLASH_CE_B (U1) or
I
I
TDI
CE
JTAG TDI connected from CPLD JTAG TDO
Active-Low Chip Enable connected from CPLD Pin
FLASH_CE1_B (U15)
42 (U1) or CPLD Pin 38 (U15)
D1
FLASH_CF_B
I
CF
Active-Low Configuration Pulse input connected to
CPLD Pin 43
B3
C2
H6
FLASH_CLKIN
FLASH_CLKOUT
FLASH_D0
I
O
O
CLK
CLKOUT
D0
Clock Input connected from Pin 1 of Header P2
Clock Output connected to Pin 5 of Header P2
SelectMAP data bit 0 connected to FPGA
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
95